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[/] [minsoc/] [branches/] [verilator/] [backend/] [spartan3a_dsp_kit/] - Rev 124

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Last modification

  • Rev 124 2011-11-02 15:27:24 GMT
  • Author: rfajardo
  • Log message:
    Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.
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[FOLDER] minsoc/ 124  4530d 04h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 124  4530d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rc-1.0/ 124  4530d 04h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  4762d 05h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4537d 03h rfajardo View Log RSS feed

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