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[/] [minsoc/] [tags/] [release-1.0/] [backend/] [spartan3e_starter_kit/] - Rev 124

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Last modification

  • Rev 124 2011-11-02 15:27:24 GMT
  • Author: rfajardo
  • Log message:
    Removing Verilog delays from minsoc_bench.v. minsoc_bench_defines.v defines now if uart or ethernet have to be tested. If yes, it checks the behavior of the enclosed firmwares. If not, simulation simply runs forever.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 124  4726d 23h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 124  4726d 23h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 42  4959d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] release-0.9/ 42  4959d 00h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4733d 21h rfajardo View Log RSS feed

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