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[/] [minsoc/] [trunk/] [bench/] - Rev 71

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  • Rev 71 2011-05-10 10:34:10 GMT
  • Author: rfajardo
  • Log message:
    Modelsim whines about missing timescales:
    -minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v

    modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a

    Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.
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[NODE][FOLDER] trunk/ 71  3430d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 70  3430d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  3430d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 71  3430d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  3479d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 70  3430d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 70  3430d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 69  3435d 09h rfajardo View Log RSS feed
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[NODE][NODE][FOLDER] utils/ 64  3437d 16h rfajardo View Log RSS feed

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