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[/] [minsoc/] [trunk/] [bench/] [verilog/] [vpi/] - Rev 2

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Last modification

  • Rev 2 2009-09-18 11:46:11 GMT
  • Author: rfajardo
  • Log message:
    First commit of project. Beta status:
    -testbench: working
    -firmware: working
    -RTL: Working for: Xilinx Spartan-3A DSP Development Kit
Path Last modification Log RSS feed
[FOLDER] minsoc/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5565d 06h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5565d 06h root View Log RSS feed
[NODE][FOLDER] trunk/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] vpi/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] dbg_comm_vpi.v 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] jp-io-vpi.vpi 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 2  5565d 04h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 2  5565d 04h rfajardo View Log RSS feed

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