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[/] [minsoc/] [trunk/] [doc/] - Rev 34

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  • Rev 34 2010-10-15 14:35:25 GMT
  • Author: rfajardo
  • Log message:
    start_server changed: '-t' option of adv_jtag_bridge for vpi connection on simulation removed. or1200_v3 will not pass on CPU self test.

    FAQ completed with asked questions since Februrary 2010.

    INSTALL informs bsdl files only have to be copied to home directory for Xilinx devices.

    synthesis_examples title includes Minimal OpenRISC System on Chip.
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[NODE][NODE][FOLDER] bench/ 28  3862d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 34  3699d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 34  3699d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] FAQ.pdf 34  3699d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] HOWTO.pdf 32  3721d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] INSTALL.pdf 34  3699d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][DB-FILE] lgpl-3.0.txt 2  4092d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] minsoc.pdf 32  3721d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] status_progress.pdf 22  3959d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] synthesis_examples.pdf 34  3699d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 33  3707d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 34  3699d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 11  4056d 22h rfajardo View Log RSS feed

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