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[/] [minsoc/] [trunk/] [prj/] [altera/] - Rev 97

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Last modification

  • Rev 97 2011-09-12 08:54:47 GMT
  • Author: rfajardo
  • Log message:
    As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board.
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[FOLDER] minsoc/ 97  4603d 02h rfajardo View Log RSS feed
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[NODE][FOLDER] tags/ 42  4783d 20h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 97  4603d 02h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 97  4603d 02h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  4728d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  4776d 20h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 97  4603d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  4603d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 96  4603d 13h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  4603d 02h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  4603d 13h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  4603d 02h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  4608d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 85  4608d 19h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  4627d 00h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 95  4604d 16h javieralso View Log RSS feed
[NODE][NODE][FOLDER] utils/ 83  4621d 01h rfajardo View Log RSS feed

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