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[/] [minsoc/] [trunk/] [rtl/] [verilog/] - Rev 163
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Last modification
- Rev 163 2012-01-26 10:02:25 GMT
- Author: rfajardo
- Log message:
- Adjusting internal initiator array widths. They were 1 bit too large. Thanks to R. Diez report.
These arrays abstract the complete initiator inputs. This way it is easier to route and arbiter using a single input.
Also removing 2 sequential delays. I didn't design them, so I can't tell if they were really useful/good.