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[/] [minsoc/] [trunk/] [rtl/] [verilog/] - Rev 70

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  • Rev 70 2011-05-10 10:06:07 GMT
  • Author: rfajardo
  • Log message:
    Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.

    Removing timescale definition of minsoc_bench_defines.v files.

    Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
    -pli ../../bench/verilog/vpi/jp-io-vpi.so
    to:
    -pli ../../bench/verilog/vpi/jp-io-vpi.dll

    These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 70  4954d 22h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5553d 22h root View Log RSS feed
[NODE][FOLDER] tags/ 42  5010d 18h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 70  4954d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 70  4954d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 69  4959d 14h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  5003d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 70  4954d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 70  4954d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] minsoc_startup/ 12  5511d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] altera_pll.v 63  4965d 15h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_clock_manager.v 62  4965d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_onchip_ram.v 7  5539d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_onchip_ram_top.v 7  5539d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_tc_top.v 7  5539d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_top.v 60  4966d 10h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_xilinx_internal_jtag.v 2  5553d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] timescale.v 70  4954d 22h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xilinx_dcm.v 62  4965d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 70  4954d 22h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 69  4959d 14h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 64  4961d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 64  4961d 21h rfajardo View Log RSS feed

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