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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [sw/] - Rev 49
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Last modification
- Rev 49 2013-02-07 18:50:35 GMT
- Author: JonasDC
- Log message:
- First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.