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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 63

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Last modification

  • Rev 63 2013-02-26 14:45:30 GMT
  • Author: JonasDC
  • Log message:
    now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 63  4166d 12h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 58  4172d 06h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 49  4185d 08h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 63  4166d 12h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 46  4253d 13h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  4253d 13h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 63  4166d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 63  4166d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 63  4166d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 45  4253d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 62  4166d 15h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 41  4263d 14h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4278d 06h JonasDC View Log RSS feed

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