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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 31

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Last modification

  • Rev 31 2012-11-07 10:01:55 GMT
  • Author: JonasDC
  • Log message:
    put first cell logic of the pipeline in a separate design unit, tested and working
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 31  3683d 06h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 1  3705d 03h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3705d 03h root View Log RSS feed
[NODE][FOLDER] trunk/ 31  3683d 06h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 26  3683d 21h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 31  3683d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 31  3683d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 31  3683d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_block.vhd 12  3697d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_n.vhd 13  3697d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] autorun_cntrl.vhd 3  3698d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b.vhd 14  3697d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_adder.vhd 9  3698d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_mux.vhd 9  3698d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] counter_sync.vhd 19  3696d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] d_flip_flop.vhd 4  3698d 07h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_primitive.vhd 3  3698d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] first_stage.vhd 18  3697d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] last_stage.vhd 18  3697d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram.vhd 3  3698d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_core.vhd 24  3687d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_pkg.vhd 31  3683d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_ctrl.vhd 24  3687d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_multiplier.vhd 25  3683d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_mult_sys_pipeline.vhd 23  3687d 07h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operands_sp.vhd 3  3698d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_dp.vhd 3  3698d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_mem.vhd 3  3698d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram.vhd 3  3698d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_1b.vhd 6  3698d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_n.vhd 15  3697d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_cell_block.vhd 17  3697d 08h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_stage.vhd 18  3697d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] stepping_logic.vhd 19  3696d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] systolic_pipeline.vhd 22  3690d 01h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_first_cell_logic.vhd 31  3683d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_last_cell_logic.vhd 30  3683d 07h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_pipeline.vhd 31  3683d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_stage.vhd 25  3683d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] x_shift_reg.vhd 21  3691d 08h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 2  3703d 03h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 31  3683d 06h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  3683d 20h JonasDC View Log RSS feed

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