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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] - Rev 36

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Last modification

  • Rev 36 2012-11-07 22:36:19 GMT
  • Author: JonasDC
  • Log message:
    found bug in new pipeline structure, now working properly. (tested in sim)
    mod_sim_exp_core uses new flexible pipeline as default.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 36  4265d 14h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 1  4287d 23h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4287d 23h root View Log RSS feed
[NODE][FOLDER] trunk/ 36  4265d 14h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 26  4266d 17h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 36  4265d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 36  4265d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 36  4265d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_block.vhd 12  4280d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] adder_n.vhd 13  4280d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] autorun_cntrl.vhd 3  4281d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b.vhd 14  4280d 18h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_adder.vhd 9  4280d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] cell_1b_mux.vhd 9  4280d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] counter_sync.vhd 19  4278d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] d_flip_flop.vhd 4  4281d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] fifo_primitive.vhd 3  4281d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] first_stage.vhd 18  4279d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] last_stage.vhd 18  4279d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] modulus_ram.vhd 3  4281d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_core.vhd 36  4265d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mod_sim_exp_pkg.vhd 34  4265d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_ctrl.vhd 24  4270d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_multiplier.vhd 32  4265d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] mont_mult_sys_pipeline.vhd 23  4270d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operands_sp.vhd 3  4281d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_dp.vhd 3  4281d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_mem.vhd 34  4265d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] operand_ram.vhd 3  4281d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_1b.vhd 6  4281d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_n.vhd 15  4280d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_cell_block.vhd 17  4280d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] standard_stage.vhd 18  4279d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] stepping_logic.vhd 19  4278d 23h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] systolic_pipeline.vhd 22  4272d 21h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_first_cell_logic.vhd 31  4266d 02h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_last_cell_logic.vhd 30  4266d 03h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_pipeline.vhd 36  4265d 14h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] sys_stage.vhd 25  4266d 17h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] x_shift_reg.vhd 21  4274d 04h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 2  4285d 23h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 35  4265d 16h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4266d 16h JonasDC View Log RSS feed

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