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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 84

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Last modification

  • Rev 84 2013-04-17 10:09:11 GMT
  • Author: JonasDC
  • Log message:
    AXI-Lite interface updated, now tested and verified on Xilinx FPGA
    renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS
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[FOLDER] mod_sim_exp/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  3495d 10h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 80  3482d 04h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 78  3482d 04h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] axi/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] plb/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 83  3455d 14h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 84  3453d 13h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  3615d 03h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 72  3495d 07h JonasDC View Log RSS feed

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