URL
https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] - Rev 2
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Last modification
- Rev 2 2012-10-18 13:14:22 GMT
- Author: JonasDC
- Log message:
- First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..