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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] [plb/] - Rev 2

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Last modification

  • Rev 2 2012-10-18 13:14:22 GMT
  • Author: JonasDC
  • Log message:
    First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 2  4179d 22h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 1  4181d 21h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4181d 21h root View Log RSS feed
[NODE][FOLDER] trunk/ 2  4179d 22h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 2  4179d 22h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 2  4179d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 2  4179d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 2  4179d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 2  4179d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] plb/ 2  4179d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] mont_mult1536.vhd 2  4179d 22h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] user_logic.vhd 2  4179d 22h JonasDC View Log RSS feed

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