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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 182
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Last modification
- Rev 182 2020-03-11 18:56:40 GMT
- Author: jshamlet
- Log message:
- Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled.