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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 209
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Last modification
- Rev 209 2020-04-09 01:40:42 GMT
- Author: jshamlet
- Log message:
- Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.