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[/] [open8_urisc/] [trunk/] [VHDL/] - Rev 210
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Last modification
- Rev 210 2020-04-09 14:27:42 GMT
- Author: jshamlet
- Log message:
- Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.