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[/] [spi_master_slave/] [trunk/] [doc/] [src/] - Rev 4

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Last modification

  • Rev 4 2011-06-16 05:37:23 GMT
  • Author: jdoin
  • Log message:
    v0.97.0068 - streamlined resets and clock enables to reduce area
    v0.97.0075 - redesigned parallel interfaces, with pipelined data transport for async clock domains
    v0.97.0083 - fixed bug "CPHA effect": redesigned SCK output circuit
    v0.97.0086 - removed master MISO input register: got 33MHz.
Path Last modification Log RSS feed
[FOLDER] spi_master_slave/ 4  4926d 17h jdoin View Log RSS feed
[NODE][FOLDER] branches/ 1  4957d 16h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4957d 16h root View Log RSS feed
[NODE][FOLDER] trunk/ 4  4926d 17h jdoin View Log RSS feed
[NODE][NODE][FOLDER] bench/ 4  4926d 17h jdoin View Log RSS feed
[NODE][NODE][FOLDER] doc/ 4  4926d 17h jdoin View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 4  4926d 17h jdoin View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] spi_master_block.bmp 2  4943d 21h jdoin View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] spi_master_block.pdf 2  4943d 21h jdoin View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] spi_master_slave_Specifications.doc 4  4926d 17h jdoin View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] SPI_MODES.jpg 2  4943d 21h jdoin View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] spi_slave_block.bmp 2  4943d 21h jdoin View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] spi_slave_block.pdf 2  4943d 21h jdoin View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 4  4926d 17h jdoin View Log RSS feed

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