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[/] [spi_master_slave/] [trunk/] [rtl/] - Rev 10

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Last modification

  • Rev 10 2011-07-17 05:21:49 GMT
  • Author: jdoin
  • Log message:
    v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
    Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.
Path Last modification Log RSS feed
[FOLDER] spi_master_slave/ 10  3420d 16h jdoin View Log RSS feed
[NODE][FOLDER] branches/ 1  3482d 14h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3482d 14h root View Log RSS feed
[NODE][FOLDER] trunk/ 10  3420d 16h jdoin View Log RSS feed
[NODE][NODE][FOLDER] bench/ 7  3424d 18h jdoin View Log RSS feed
[NODE][NODE][FOLDER] doc/ 7  3424d 18h jdoin View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 10  3420d 16h jdoin View Log RSS feed
[NODE][NODE][NODE][DB-FILE] readme.txt 10  3420d 16h jdoin View Log RSS feed
[NODE][NODE][NODE][FILE] spi_loopback.ucf 5  3426d 16h jdoin View Log RSS feed
[NODE][NODE][NODE][FILE] spi_loopback.vhd 10  3420d 16h jdoin View Log RSS feed
[NODE][NODE][NODE][FILE] spi_master.vhd 10  3420d 16h jdoin View Log RSS feed
[NODE][NODE][NODE][FILE] spi_slave.vhd 10  3420d 16h jdoin View Log RSS feed
[NODE][NODE][FOLDER] syn/ 10  3420d 16h jdoin View Log RSS feed

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