URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [rtl/] - Rev 10

Rev 10 2011-07-17 05:21:49 GMT
Author: jdoin
Log message:
v1.11.0080: Changed sampling of MISO in spi_master.vhd (removed the input register).
Verified master+slave cores in silicon on a Spartan-6 FPGA at 100MHz, using Xilinx ISE 13.1 and a Digilent Atlys board. Project is included in trunk/syn/spi_master_atlys.xise.

Path	Last modification			Log	RSS feed
spi_master_slave/	10	4837d 12h	jdoin	View Log	RSS feed
branches/	1	4899d 10h	root	View Log	RSS feed
tags/	1	4899d 10h	root	View Log	RSS feed
trunk/	10	4837d 12h	jdoin	View Log	RSS feed
bench/	7	4841d 14h	jdoin	View Log	RSS feed
doc/	7	4841d 14h	jdoin	View Log	RSS feed
rtl/	10	4837d 12h	jdoin	View Log	RSS feed
readme.txt	10	4837d 12h	jdoin	View Log	RSS feed
spi_loopback.ucf	5	4843d 11h	jdoin	View Log	RSS feed
spi_loopback.vhd	10	4837d 12h	jdoin	View Log	RSS feed
spi_master.vhd	10	4837d 12h	jdoin	View Log	RSS feed
spi_slave.vhd	10	4837d 12h	jdoin	View Log	RSS feed
syn/	10	4837d 12h	jdoin	View Log	RSS feed