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URL https://opencores.org/ocsvn/uart2bus/uart2bus/trunk

Subversion Repositories uart2bus

[/] [uart2bus/] [trunk/] [verilog/] [rtl/] - Rev 14

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Last modification

  • Rev 12 2012-02-25 10:48:40 GMT
  • Author: motilito
  • Log message:
    Updated Verilog implementation to sync with VHDL to include internal bus request/grant mechanism.
Path Last modification Log RSS feed
[FOLDER] uart2bus/ 14  2648d 12h motilito View Log RSS feed
[NODE][FOLDER] branches/ 1  5180d 21h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5180d 21h root View Log RSS feed
[NODE][FOLDER] trunk/ 14  2648d 12h motilito View Log RSS feed
[NODE][NODE][FOLDER] doc/ 12  4438d 05h motilito View Log RSS feed
[NODE][NODE][FOLDER] scilab/ 7  4775d 19h motilito View Log RSS feed
[NODE][NODE][FOLDER] verilog/ 12  4438d 05h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 12  4438d 05h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 12  4438d 05h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] baud_gen.v 3  5178d 02h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart2bus_top.v 12  4438d 05h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_parser.v 12  4438d 05h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_rx.v 9  4533d 05h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_top.v 2  5178d 03h motilito View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_tx.v 9  4533d 05h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 4  5131d 20h motilito View Log RSS feed
[NODE][NODE][NODE][FOLDER] syn/ 2  5178d 03h motilito View Log RSS feed
[NODE][NODE][FOLDER] vhdl/ 13  2982d 01h smuller View Log RSS feed

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