OpenCores
URL https://opencores.org/ocsvn/zipcpu/zipcpu/trunk

Subversion Repositories zipcpu

[/] [zipcpu/] [trunk/] [rtl/] - Rev 138

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 138 2016-05-06 14:54:30 GMT
  • Author: dgisselq
  • Log message:
    This updates the CPU multiply instruction into a set of three instructions.
    MPY is a 32x32-bit multiply instruction, returning the low 32-bit result,
    MPYUHI returns the upper 32-bits assuming the result was unsigned and MPYSHI
    returns the upper 32-bits assuming the result was signed.
Path Last modification Log RSS feed
[FOLDER] zipcpu/ 138  3073d 09h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  3358d 07h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3358d 07h root View Log RSS feed
[NODE][FOLDER] trunk/ 138  3073d 09h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 134  3087d 23h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 107  3126d 01h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 138  3073d 09h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 69  3209d 08h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 138  3073d 09h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 88  3196d 01h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] cpudefs.v 138  3073d 09h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 105  3131d 08h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipbones.v 105  3131d 08h dgisselq View Log RSS feed
[NODE][NODE][NODE][FILE] zipsystem.v 128  3088d 00h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 138  3073d 09h dgisselq View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.