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[/] [zipcpu/] [trunk/] [rtl/] [core/] - Rev 38

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Last modification

  • Rev 38 2015-09-29 16:38:09 GMT
  • Author: dgisselq
  • Log message:
    A couple of quick updates:

    - The Zip CPU now supports pipelined memory access at one clock per
    instruction (assuming all the instructions are in the cache)
    - There is now a 'zipbones' module to build a Zip System without peripherals.
    Any peripherals would then need to be external to the CPU.
    - Some bug fixes.

    Documentation changes coming shortly.
Path Last modification Log RSS feed
[FOLDER] zipcpu/ 38  2432d 20h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  2497d 20h root View Log RSS feed
[NODE][FOLDER] tags/ 1  2497d 20h root View Log RSS feed
[NODE][FOLDER] trunk/ 38  2432d 20h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 36  2441d 23h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 37  2441d 11h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 38  2432d 20h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 36  2441d 23h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 38  2432d 20h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] cpuops.v 25  2471d 12h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] memops.v 36  2441d 23h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pipefetch.v 38  2432d 20h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pipemem.v 38  2432d 20h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] prefetch.v 36  2441d 23h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] zipcpu.v 38  2432d 20h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 36  2441d 23h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 36  2441d 23h dgisselq View Log RSS feed

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