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[/] [zipcpu/] [trunk/] [rtl/] [core/] - Rev 65

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  • Rev 65 2015-10-22 15:59:30 GMT
  • Author: dgisselq
  • Log message:
    Lots of logic simplifications to the core, in addition to better support for
    illegal instruction detection and bus error detection. The biggest change
    had to deal with pushing the debug write interface into the ALU write
    processing path. This simplifies the logic of adjusting the PC and CC
    registers primarily, but also any writes to other registers. It also delays
    these register writes by a clock, but since the debug interface is already
    ridiculously slow I doubt that matters any.
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[FOLDER] zipcpu/ 65  2448d 02h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  2536d 02h root View Log RSS feed
[NODE][FOLDER] tags/ 1  2536d 02h root View Log RSS feed
[NODE][FOLDER] trunk/ 65  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 58  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 49  2467d 20h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 65  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] aux/ 61  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] core/ 65  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] cpuops.v 62  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] memops.v 48  2467d 20h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pipefetch.v 63  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] pipemem.v 63  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] prefetch.v 63  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] zipcpu.v 65  2448d 02h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] peripherals/ 56  2458d 04h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 60  2448d 02h dgisselq View Log RSS feed

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