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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 114

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Rev Log message Author Age Path
114 CRC generation iand verification in bench changed. mohor 7555d 20h /dbg_interface/tags/rel_21/bench/verilog
113 IDCODE test improved. mohor 7555d 21h /dbg_interface/tags/rel_21/bench/verilog
112 dbg_tb_defines.v not used. mohor 7556d 16h /dbg_interface/tags/rel_21/bench/verilog
111 Define tap_defines.v added to test bench. mohor 7556d 16h /dbg_interface/tags/rel_21/bench/verilog
110 Waiting for "ready" improved. mohor 7556d 17h /dbg_interface/tags/rel_21/bench/verilog
102 New version. mohor 7558d 11h /dbg_interface/tags/rel_21/bench/verilog
101 Almost finished. mohor 7558d 12h /dbg_interface/tags/rel_21/bench/verilog
99 cpu registers added. mohor 7559d 15h /dbg_interface/tags/rel_21/bench/verilog
96 Working. mohor 7560d 19h /dbg_interface/tags/rel_21/bench/verilog
95 Temp version. mohor 7561d 06h /dbg_interface/tags/rel_21/bench/verilog
93 tmp version. mohor 7562d 18h /dbg_interface/tags/rel_21/bench/verilog
92 temp version. mohor 7565d 22h /dbg_interface/tags/rel_21/bench/verilog
91 tmp version. mohor 7566d 17h /dbg_interface/tags/rel_21/bench/verilog
90 tmp version. mohor 7567d 12h /dbg_interface/tags/rel_21/bench/verilog
89 temp4 version. mohor 7568d 17h /dbg_interface/tags/rel_21/bench/verilog
88 temp3 version. mohor 7569d 12h /dbg_interface/tags/rel_21/bench/verilog
87 tmp2 version. mohor 7570d 17h /dbg_interface/tags/rel_21/bench/verilog
80 New version of the debug interface. Not finished, yet. mohor 7583d 15h /dbg_interface/tags/rel_21/bench/verilog
75 Simulation files. mohor 7644d 13h /dbg_interface/tags/rel_21/bench/verilog
73 CRC logic changed. mohor 7644d 13h /dbg_interface/tags/rel_21/bench/verilog
63 Three more chains added for cpu debug access. simons 7700d 16h /dbg_interface/tags/rel_21/bench/verilog
47 mon_cntl_o signals that controls monitor mux added. mohor 8178d 15h /dbg_interface/tags/rel_21/bench/verilog
38 Few outputs for boundary scan chain added. mohor 8234d 15h /dbg_interface/tags/rel_21/bench/verilog
36 Structure changed. Hooks for jtag chain added. mohor 8238d 14h /dbg_interface/tags/rel_21/bench/verilog
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8378d 18h /dbg_interface/tags/rel_21/bench/verilog
15 bs_chain_o added. mohor 8380d 19h /dbg_interface/tags/rel_21/bench/verilog
13 Signal names changed to lowercase. mohor 8381d 19h /dbg_interface/tags/rel_21/bench/verilog
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8382d 20h /dbg_interface/tags/rel_21/bench/verilog
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8403d 15h /dbg_interface/tags/rel_21/bench/verilog
9 Working version. Few bugs fixed, comments added. mohor 8407d 19h /dbg_interface/tags/rel_21/bench/verilog

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