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[/] [ethmac/] [tags/] [rel_26/] [bench/] [verilog/] [tb_ethernet.v] - Rev 322

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322 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7458d 23h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
318 Latest Ethernet IP core testbench. tadejm 7489d 22h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
315 Updated testbench. Some more testcases, some repaired. tadejm 7602d 01h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
302 mbist signals updated according to newest convention markom 7651d 06h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
299 Artisan RAMs added. mohor 7709d 02h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7909d 22h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
279 Underrun test fixed. Many other tests fixed. mohor 7911d 01h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
274 Backup version. Not fully working. tadejm 7918d 19h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
267 Full duplex control frames tested. mohor 7974d 22h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
266 Flow control test almost finished. mohor 7979d 21h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7980d 12h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7981d 00h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
254 Temp version. mohor 7982d 18h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
252 Just some updates. tadejm 7982d 21h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
243 Late collision is not reported any more. tadejm 7988d 01h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
227 Changed BIST scan signals. tadejm 8014d 21h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
223 Some code changed due to bug fixes. tadejm 8015d 00h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 8024d 01h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
194 Full duplex tests modified and testbench bug repaired. tadej 8043d 00h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
192 Some additional reports added tadej 8044d 20h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
182 Full duplex test improved. tadej 8046d 20h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
181 MIIM test look better. mohor 8046d 23h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
180 Bench outputs data to display every 128 bytes. mohor 8049d 19h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
179 Beautiful tests merget together mohor 8049d 20h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
178 Rearanged testcases mohor 8049d 20h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
177 Bug in MIIM fixed. mohor 8049d 23h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
170 Headers changed. mohor 8050d 02h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 8050d 02h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
158 Typo fixed. mohor 8054d 22h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v
156 Valid testbench. mohor 8057d 03h /ethmac/tags/rel_26/bench/verilog/tb_ethernet.v

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