Rev |
Log message |
Author |
Age |
Path |
51 |
true dual port ram for xilinx |
JonasDC |
4238d 05h |
/mod_sim_exp/trunk/rtl/vhdl |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4238d 05h |
/mod_sim_exp/trunk/rtl/vhdl |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4318d 05h |
/mod_sim_exp/trunk/rtl/vhdl |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4321d 22h |
/mod_sim_exp/trunk/rtl/vhdl |
43 |
made the core parameters generics |
JonasDC |
4321d 22h |
/mod_sim_exp/trunk/rtl/vhdl |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4328d 06h |
/mod_sim_exp/trunk/rtl/vhdl |
41 |
removed deprecated files from version control |
JonasDC |
4328d 06h |
/mod_sim_exp/trunk/rtl/vhdl |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4336d 10h |
/mod_sim_exp/trunk/rtl/vhdl |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4336d 21h |
/mod_sim_exp/trunk/rtl/vhdl |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4337d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4341d 00h |
/mod_sim_exp/trunk/rtl/vhdl |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4341d 20h |
/mod_sim_exp/trunk/rtl/vhdl |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4341d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
33 |
default pipeline changed to old version, there seems to be an occasional error with new version. |
JonasDC |
4342d 02h |
/mod_sim_exp/trunk/rtl/vhdl |
32 |
new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. |
JonasDC |
4342d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4342d 08h |
/mod_sim_exp/trunk/rtl/vhdl |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4342d 09h |
/mod_sim_exp/trunk/rtl/vhdl |
25 |
first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline |
JonasDC |
4342d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4346d 08h |
/mod_sim_exp/trunk/rtl/vhdl |
23 |
added descriptive comments |
JonasDC |
4346d 09h |
/mod_sim_exp/trunk/rtl/vhdl |
22 |
updated the systolic pipeline with descriptive signal names and comments |
JonasDC |
4349d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
21 |
changed x_i signal to xi |
JonasDC |
4350d 10h |
/mod_sim_exp/trunk/rtl/vhdl |
20 |
added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules |
JonasDC |
4350d 10h |
/mod_sim_exp/trunk/rtl/vhdl |
19 |
updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic |
JonasDC |
4355d 05h |
/mod_sim_exp/trunk/rtl/vhdl |
18 |
updated stages with comments and renamed some signals for consistency |
JonasDC |
4356d 05h |
/mod_sim_exp/trunk/rtl/vhdl |
17 |
updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules |
JonasDC |
4356d 10h |
/mod_sim_exp/trunk/rtl/vhdl |
16 |
package with modified generic parameter for register_n |
JonasDC |
4356d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
15 |
changed generic for register width from n to width for consistency |
JonasDC |
4356d 23h |
/mod_sim_exp/trunk/rtl/vhdl |
14 |
changed comments, file is now according to OC design rules |
JonasDC |
4357d 00h |
/mod_sim_exp/trunk/rtl/vhdl |
13 |
added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules |
JonasDC |
4357d 00h |
/mod_sim_exp/trunk/rtl/vhdl |