OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] - Rev 96

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
96 Update! mihad 7778d 06h /
95 Removed this file, because it was too large - long download time. mihad 7778d 06h /
94 Changed one critical PCI bus signal logic. mihad 7778d 06h /
93 Added a test application! mihad 7778d 13h /
92 Update! mihad 7778d 13h /
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7814d 03h /
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7814d 03h /
89 Burst 2 error fixed. mihad 7850d 04h /
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7856d 03h /
87 Updated acording to RTL changes. mihad 7868d 00h /
86 Entered the option to disable no response counter in wb master. mihad 7868d 00h /
85 Changed Vendor ID defines. mihad 7868d 05h /
84 Changed vendor ID. mihad 7871d 23h /
83 Cleaned up the code. No functional changes. mihad 7896d 21h /
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7910d 18h /
81 Updated synchronization in top level fifo modules. mihad 7910d 18h /
80 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7913d 23h /
79 Updated. mihad 7913d 23h /
78 Old files with wrong names removed. mihad 7913d 23h /
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7913d 23h /
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7916d 23h /
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7919d 23h /
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7920d 00h /
73 Bug fixes, testcases added. mihad 7920d 00h /
72 *** empty log message *** mihad 7967d 04h /
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7974d 19h /
70 This commit was manufactured by cvs2svn to create tag 'rel_2'. 8012d 03h /
69 Changed BIST signal names etc.. mihad 8012d 03h /
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8015d 12h /
67 Changed BIST signals for RAMs. tadejm 8015d 17h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.