URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 107

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
107	- Added new example for memory testing.	cwalter	6463d 04h	/
106	- ALUOP1_LD_MEM_BIT must be checked within ALUOP1_WB_REG_BIT.	cwalter	6463d 04h	/
105	- OPCODE_ST_DISP must not set ALUOP1_WB_REG_BIT.	cwalter	6463d 04h	/
104	- Added missing signal dmem_data_in.	cwalter	6463d 05h	/
103	- Added simulation for memory to behavioral. - Added empty mif file for memory.	cwalter	6463d 05h	/
102	changed data pitch	ustadler	6465d 09h	/
101	- Signals for memory block where not always set. This resulted in a latch.	cwalter	6465d 10h	/
100	- Signal clear_in was missing in sensitivity list.	cwalter	6465d 10h	/
99	- Fixed problem with barrel shifter input signals where a latch has been synthesized.	cwalter	6465d 10h	/
98	- Applied indenting tool.	cwalter	6465d 10h	/
97	Fixed bug: only set branch and clear signals if branch is actually executed.	jlechner	6465d 11h	/
96	- SR register is now computed in ALU stage.	cwalter	6465d 11h	/
95	- Write back now only updates SR in case of a LOAD.	cwalter	6465d 11h	/
94	Added signal from ex stage to register lock unit for clearing all register locks when a branch is executed.	jlechner	6465d 11h	/
93	Changed behavior on branch. Current PC is immeadiately taken from ex stage alu result.	jlechner	6465d 12h	/
92	Added logic for inserting a nop instruction when the pipeline is cleared.	jlechner	6465d 12h	/
91	- Computed new SR values from ALU result.	cwalter	6465d 12h	/
90	Added output signal for clearing all register locks when a branch instruction is executed. This is necessary because the id stage could have locked registers for an instruction that is cleared out of the pipeline due to the branch.	jlechner	6465d 12h	/
89	Added input signal for clearing all register locks.	jlechner	6465d 12h	/
88	- Added new patch for assembler.	cwalter	6465d 12h	/
87	no message	cwalter	6465d 12h	/
86	- Added new example for a more complex loop.	cwalter	6465d 12h	/
85	Removed PC reset on clear_in signal. Clear_in only comes together with a branch, so it is sufficient branch immediately.	jlechner	6465d 15h	/
84	- PC value was wrong.	cwalter	6465d 15h	/
83	- sr_enable and lr_enable where incorrect.	cwalter	6465d 15h	/
82	- Updated drawings for memory.	cwalter	6465d 15h	/
81	- Changed to include barrel shifter.	cwalter	6465d 15h	/
80	- Fixed testbench to work with new barrel shifter.	cwalter	6465d 15h	/
79	- Added barrel shifter.	cwalter	6465d 15h	/
78	Added stall_in to sensitivity list.	jlechner	6465d 15h	/

Browse

Tools

Subversion Repositories rise

[/] - Rev 107

Filtering Options