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Rev Log message Author Age Path
43 *** empty log message *** jesus 7978d 00h /
42 Fixed bus req/ack cycle jesus 7978d 01h /
41 Removed UNISIM library jesus 7978d 01h /
40 Cleanup jesus 7978d 01h /
39 Added -n option and component declaration jesus 8005d 22h /
38 Added Leonardo .ucf generation jesus 8005d 22h /
37 Changed to single register file jesus 8006d 01h /
36 Added component declaration jesus 8006d 01h /
35 Release 0242 jesus 8012d 13h /
34 Updated for ISE 5.1 jesus 8012d 18h /
33 Fixed typo jesus 8022d 10h /
32 Fixed for ISE 5.1 jesus 8022d 10h /
31 Fixed generic name error jesus 8025d 12h /
30 Changed to xilinx specific RAM jesus 8031d 12h /
29 Fixed (IX/IY+d) timing and added all GB op-codes jesus 8031d 12h /
28 Adapted for zxgate jesus 8032d 12h /
27 Xilinx SSRAM, initial release jesus 8032d 12h /
26 Fixed instruction timing for POP and DJNZ jesus 8046d 04h /
25 IX/IY timing and ADC/SBC fix jesus 8047d 14h /
24 no message jesus 8053d 10h /
23 Fixed T2Write jesus 8053d 10h /
22 Added 8080 top level jesus 8053d 11h /
21 no message jesus 8058d 10h /
20 Updated for new T80s generic jesus 8058d 10h /
19 Initial version jesus 8058d 10h /
18 Added T2Write generic jesus 8058d 16h /
17 Removed write through jesus 8060d 09h /
16 no message jesus 8060d 13h /
15 Added clock enable and fixed IM 2 jesus 8067d 12h /
14 Changed to Xilinx ROM jesus 8087d 00h /

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