URL https://opencores.org/ocsvn/tv80/tv80/trunk

Subversion Repositories tv80

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Rev	Log message	Author	Age	Path
98	Changed malloc for strings with constant length copy, add assertion checks for null pointers in env memory, and fixed some formatting	ghutchis	5406d 14h	/
97	Added data in mux, added 16450 UART to environment	ghutchis	5410d 17h	/
96	Added Z80 op decode to environment, enabled by -k switch	ghutchis	5410d 23h	/
95	Updated regression script to use SystemC simulation	ghutchis	5412d 18h	/
94	Ported over env_io.v from Verilog environment to tv_responder. Basic tests from Verilog environment (hello, fib) now passing in SystemC environment.	ghutchis	5414d 19h	/
93	Added common header file for all systemc environment	ghutchis	5415d 17h	/
92	Added responder to top level, beginning of support for ihex load	ghutchis	5419d 19h	/
91	Preliminary support for SystemC/Verilator environment	ghutchis	5419d 21h	/
90	Fixed syntax errors in core preventing Verilator from compiling. Added new capability to register generator to make registers which latch on an external event. Removed spurious copyright notice.	ghutchis	5419d 21h	/
89	RTL and environment fixes for nmi bug	ghutchis	5440d 00h	/
88	Fixed bug introduced by conversion of mcycle to one-hot FSM	ghutchis	5441d 15h	/
87	Added additional ifdef signals to remove unneede R (refresh) register	ghutchis	5456d 22h	/
86	Added old uploaded documents to new repository.	root	5680d 04h	/
85	Added old uploaded documents to new repository.	root	5680d 10h	/
84	New directory structure.	root	5680d 10h	/
83	Some fixes from Guy-- replace case with casex.	hharte	5753d 16h	/
82	Clean up spacing	hharte	5763d 12h	/
81	Initial version of TV80 Wishbone Wrapper	hharte	5763d 13h	/
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6863d 01h	/
79	Added JR self-checking test	ghutchis	6863d 01h	/
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6906d 03h	/
77	Added back files lost after server crash	ghutchis	6937d 20h	/
76	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		7017d 03h	/
75	Modified environment I/O so multicycle wr_n signals are only seen as a single write.	ghutchis	7017d 03h	/
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	7017d 04h	/
73	Added RC4 encrypt/decrypt test	ghutchis	7028d 22h	/
72	Added copyright header	ghutchis	7028d 22h	/
71	Ported UART from T80	ghutchis	7090d 02h	/
70	Added test for T16450 UART	ghutchis	7140d 21h	/
69	Added UART instance in testbench, and added UART to compile list.	ghutchis	7140d 21h	/

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Subversion Repositories tv80

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