OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [tags/] [AEMB_711/] [rtl/] - Rev 62

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
62 Fixed minor typo. sybreon 6161d 05h /aemb/tags/AEMB_711/rtl/
61 Changed interrupt handling system (reported by M. Ettus). sybreon 6161d 06h /aemb/tags/AEMB_711/rtl/
56 Parameterised optional components into aeMB_xecu.v sybreon 6165d 04h /aemb/tags/AEMB_711/rtl/
55 Upgraded license to LGPLv3.
Significant performance optimisations.		 sybreon 6165d 12h /aemb/tags/AEMB_711/rtl/
53 Added GET/PUT support through a FSL bus. sybreon 6166d 08h /aemb/tags/AEMB_711/rtl/
51 Fixed data WISHBONE arbitration problem (reported by J Lee). sybreon 6167d 11h /aemb/tags/AEMB_711/rtl/
50 Parameterised optional components. sybreon 6167d 14h /aemb/tags/AEMB_711/rtl/
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6171d 23h /aemb/tags/AEMB_711/rtl/
45 Minor code cleanup. sybreon 6172d 20h /aemb/tags/AEMB_711/rtl/
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6173d 09h /aemb/tags/AEMB_711/rtl/
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6174d 01h /aemb/tags/AEMB_711/rtl/
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6184d 09h /aemb/tags/AEMB_711/rtl/
38 Added interrupt support. sybreon 6329d 10h /aemb/tags/AEMB_711/rtl/
36 Removed asynchronous reset signal. sybreon 6342d 20h /aemb/tags/AEMB_711/rtl/
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6343d 16h /aemb/tags/AEMB_711/rtl/
34 Corrected speed issues after rev 1.9 update. sybreon 6344d 06h /aemb/tags/AEMB_711/rtl/
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6359d 13h /aemb/tags/AEMB_711/rtl/
31 Removed byte acrobatics. sybreon 6359d 13h /aemb/tags/AEMB_711/rtl/
28 Fixed simulation bug. sybreon 6362d 13h /aemb/tags/AEMB_711/rtl/
27 Removed some unnecessary bubble control. sybreon 6363d 00h /aemb/tags/AEMB_711/rtl/
26 Fixed minor synthesis bug. sybreon 6363d 00h /aemb/tags/AEMB_711/rtl/
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6363d 04h /aemb/tags/AEMB_711/rtl/
24 Made minor performance optimisations. sybreon 6363d 14h /aemb/tags/AEMB_711/rtl/
23 Fixed minor simulation bug. sybreon 6364d 06h /aemb/tags/AEMB_711/rtl/
22 Added support for 8-bit and 16-bit data types. sybreon 6364d 06h /aemb/tags/AEMB_711/rtl/
19 Added initial unified memory core. sybreon 6376d 16h /aemb/tags/AEMB_711/rtl/
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6377d 08h /aemb/tags/AEMB_711/rtl/
17 Cosmetic changes sybreon 6378d 12h /aemb/tags/AEMB_711/rtl/
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6379d 00h /aemb/tags/AEMB_711/rtl/
14 Added initial interrupt/exception support. sybreon 6385d 14h /aemb/tags/AEMB_711/rtl/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.