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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] [openmsp430/] - Rev 176

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176 Update FPGA projects with latest openMSP430 core RTL olivier.girard 4257d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
155 Update FPGA projects with the latest openMSP430 verilog code. olivier.girard 4364d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4449d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4452d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
136 Update all FPGA projects with the latest core version. olivier.girard 4571d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
132 Update FPGA examples with the POP.B bug fix olivier.girard 4584d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4668d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
112 Modified comment. olivier.girard 4877d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4878d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
109 Update Xilinx FPGA example with the latest openMSP430 core RTL version. olivier.girard 4932d 23h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4949d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
104 Update all FPGA example projects with the latest RTL version. olivier.girard 4953d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
91 Fixed bug when an IRQ arrives while CPU is halted through the serial debug interface.
This bug is CRITICAL for people using working with interrupts and the Serial Debug Interface.		 olivier.girard 4967d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
86 Update serial debug interface test patterns to make them work with all program memory configurations. olivier.girard 4990d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
85 Diverse RTL cosmetic updates. olivier.girard 4990d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 4995d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
79 Update the GPIO peripheral to fix a potential synchronization issue. olivier.girard 5056d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
74 Update serial debug interface to support memories with a size which is not a power of 2.
Update the software tools accordingly.		 olivier.girard 5143d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
72 Expand configurability options of the program and data memory sizes. olivier.girard 5170d 16h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
71 Update the FPGA example projects with the newer openMSP430 core including the hardware multiplier. olivier.girard 5317d 15h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
61 Update openMSP430 rtl. olivier.girard 5349d 13h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
59 Update the FPGA projects with the latest core design updates. olivier.girard 5351d 12h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5356d 17h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
37 olivier.girard 5385d 14h /openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/
33 In order to avoid confusion, the following changes have been implemented to the Verilog code:
- renamed the "rom_*" ports and defines to "pmem_*" (program memory).
- renamed the "ram_*" ports and defines to "dmem_*" (data memory).

In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.		 olivier.girard 5385d 17h /openmsp430/trunk/core/rtl/verilog/
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).		 olivier.girard 5506d 19h /openmsp430/trunk/core/rtl/verilog/
17 Updated header with SVN info olivier.girard 5532d 14h /openmsp430/trunk/core/rtl/verilog/
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5567d 14h /openmsp430/trunk/core/rtl/verilog/

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