OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] - Rev 89

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
89 Burst 2 error fixed. mihad 7822d 23h /pci/tags/rel_11/
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7828d 22h /pci/tags/rel_11/
87 Updated acording to RTL changes. mihad 7840d 20h /pci/tags/rel_11/
86 Entered the option to disable no response counter in wb master. mihad 7840d 20h /pci/tags/rel_11/
85 Changed Vendor ID defines. mihad 7841d 00h /pci/tags/rel_11/
84 Changed vendor ID. mihad 7844d 18h /pci/tags/rel_11/
83 Cleaned up the code. No functional changes. mihad 7869d 17h /pci/tags/rel_11/
81 Updated synchronization in top level fifo modules. mihad 7883d 13h /pci/tags/rel_11/
79 Updated. mihad 7886d 18h /pci/tags/rel_11/
78 Old files with wrong names removed. mihad 7886d 19h /pci/tags/rel_11/
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7886d 19h /pci/tags/rel_11/
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7889d 18h /pci/tags/rel_11/
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7892d 19h /pci/tags/rel_11/
73 Bug fixes, testcases added. mihad 7892d 19h /pci/tags/rel_11/
72 *** empty log message *** mihad 7939d 23h /pci/tags/rel_11/
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7947d 15h /pci/tags/rel_11/
69 Changed BIST signal names etc.. mihad 7984d 22h /pci/tags/rel_11/
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7988d 08h /pci/tags/rel_11/
67 Changed BIST signals for RAMs. tadejm 7988d 13h /pci/tags/rel_11/
66 Changed empty status generation in pciw_fifo_control.v mihad 7991d 23h /pci/tags/rel_11/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7994d 21h /pci/tags/rel_11/
64 The testcase I just added in previous revision repaired mihad 7994d 23h /pci/tags/rel_11/
63 Added additional testcase and changed rst name in BIST to trst mihad 7995d 01h /pci/tags/rel_11/
62 Added BIST signals for RAMs. mihad 7997d 18h /pci/tags/rel_11/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8005d 18h /pci/tags/rel_11/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8005d 19h /pci/tags/rel_11/
58 Removed all logic from asynchronous reset network mihad 8010d 19h /pci/tags/rel_11/
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8011d 01h /pci/tags/rel_11/
56 Number of state bits define was removed mihad 8011d 16h /pci/tags/rel_11/
55 Changed state machine encoding to true one-hot mihad 8011d 17h /pci/tags/rel_11/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.