OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] - Rev 56

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
56 Number of state bits define was removed mihad 8038d 10h /pci/tags/rel_WB_B3/
55 Changed state machine encoding to true one-hot mihad 8038d 10h /pci/tags/rel_WB_B3/
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8071d 12h /pci/tags/rel_WB_B3/
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8071d 15h /pci/tags/rel_WB_B3/
52 Oops, never before noticed that OC header is missing mihad 8071d 19h /pci/tags/rel_WB_B3/
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8071d 20h /pci/tags/rel_WB_B3/
50 Got rid of undef directives mihad 8074d 12h /pci/tags/rel_WB_B3/
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8074d 12h /pci/tags/rel_WB_B3/
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8074d 12h /pci/tags/rel_WB_B3/
47 Known issues repaired mihad 8074d 18h /pci/tags/rel_WB_B3/
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8079d 12h /pci/tags/rel_WB_B3/
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8080d 18h /pci/tags/rel_WB_B3/
44 Added for testing of Configuration Cycles Type 1 mihad 8080d 18h /pci/tags/rel_WB_B3/
43 Removed - Interrupt acknowledge cycle now accepted by pci_behaviorial_device mihad 8080d 18h /pci/tags/rel_WB_B3/
42 Removed out of date files mihad 8092d 19h /pci/tags/rel_WB_B3/
40 From these Wrod files PDF were created - added future improvements tadej 8171d 09h /pci/tags/rel_WB_B3/
39 File not needed tadej 8171d 10h /pci/tags/rel_WB_B3/
38 This file is not needed tadej 8171d 13h /pci/tags/rel_WB_B3/
37 These files are not needed any more tadej 8171d 13h /pci/tags/rel_WB_B3/
36 *** empty log message *** tadej 8171d 14h /pci/tags/rel_WB_B3/
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8225d 21h /pci/tags/rel_WB_B3/
34 Added missing include statements mihad 8240d 19h /pci/tags/rel_WB_B3/
33 Added some testcases, removed un-needed fifo signals mihad 8241d 17h /pci/tags/rel_WB_B3/
32 Added include statement that was missing and causing errors mihad 8249d 13h /pci/tags/rel_WB_B3/
31 User defined constants used for Test Application tadej 8252d 08h /pci/tags/rel_WB_B3/
30 Example of PCI testbench log file mihad 8252d 17h /pci/tags/rel_WB_B3/
29 Xilinx synthesys log file tadej 8252d 19h /pci/tags/rel_WB_B3/
28 pci/doc/pci_databook.pdf tadej 8253d 14h /pci/tags/rel_WB_B3/
27 Modified testbench and fixed some bugs mihad 8255d 12h /pci/tags/rel_WB_B3/
26 Modified testbench and fixed some bugs mihad 8255d 12h /pci/tags/rel_WB_B3/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.