OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 258

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
258 Fixed the input parametric testing logic, removed a pad. creep 5508d 09h /t6507lp/trunk/rtl/verilog/
255 Changed the PADS verilog description to minimize violations creep 5530d 11h /t6507lp/trunk/rtl/verilog/
254 Fixed a latch in the design creep 5530d 12h /t6507lp/trunk/rtl/verilog/
253 Changed the rw_mem signal name in the hierarchy creep 5553d 12h /t6507lp/trunk/rtl/verilog/
252 Added a stubs file for the pads. creep 5553d 12h /t6507lp/trunk/rtl/verilog/
251 Added the io wrapper creep 5553d 15h /t6507lp/trunk/rtl/verilog/
246 Added some older files plus the first syn script creep 5560d 15h /t6507lp/trunk/rtl/verilog/
243 Fixing STA_IDY bug creep 5602d 08h /t6507lp/trunk/rtl/verilog/
242 Bug regardind the STA_IDY opcode creep 5602d 11h /t6507lp/trunk/rtl/verilog/
239 Zero flag fixed for SBC while in Decimal Mode. Bug #34. gabrieloshiro 5603d 13h /t6507lp/trunk/rtl/verilog/
238 ALU file is linted. creep 5606d 10h /t6507lp/trunk/rtl/verilog/
237 Added a preliminary collision detection logic. creep 5607d 12h /t6507lp/trunk/rtl/verilog/
236 Added the video converter testbench to the repository. creep 5607d 15h /t6507lp/trunk/rtl/verilog/
235 Bug #60: added a brief simulation to the video_converter module. creep 5608d 08h /t6507lp/trunk/rtl/verilog/
234 SBC Decimal mode 100% verified. creep 5613d 10h /t6507lp/trunk/rtl/verilog/
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 5613d 14h /t6507lp/trunk/rtl/verilog/
232 New video test. creep 5615d 08h /t6507lp/trunk/rtl/verilog/
231 Minor bugs fixed. gabrieloshiro 5615d 10h /t6507lp/trunk/rtl/verilog/
230 Changed TIA behavior. It is now pixel-based. creep 5615d 10h /t6507lp/trunk/rtl/verilog/
229 Created a one-line pattern. creep 5615d 15h /t6507lp/trunk/rtl/verilog/
228 gabrieloshiro 5615d 15h /t6507lp/trunk/rtl/verilog/
227 Fixing conflicts. creep 5615d 15h /t6507lp/trunk/rtl/verilog/
226 work plz creep 5615d 15h /t6507lp/trunk/rtl/verilog/
225 Minor changes! gabrieloshiro 5616d 07h /t6507lp/trunk/rtl/verilog/
224 Added a top level for the tests. creep 5616d 09h /t6507lp/trunk/rtl/verilog/
223 Minor sintax errors fixed. gabrieloshiro 5616d 10h /t6507lp/trunk/rtl/verilog/
222 Added a simple line-by-line tester. creep 5616d 11h /t6507lp/trunk/rtl/verilog/
221 Added a VGA controller. creep 5616d 15h /t6507lp/trunk/rtl/verilog/
220 Bug #59: video converter done. creep 5617d 09h /t6507lp/trunk/rtl/verilog/
219 Video YPbPr to RGB is coded. creep 5620d 08h /t6507lp/trunk/rtl/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.