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21 Fix overrun and underrun interrupts bug

The overrun and underrun did not have any logic for
resetting their signals, this patch changes that so
that the interrupt signal is only on when the event
happens. The interrupt will be latched into
the interrupt status register anyway, so keeping it
high for (in worst case) one clock cycle is enough.
stekern 4826d 16h /
20 root 5624d 03h /
19 root 5680d 05h /
18 Added old uploaded documents to new repository. root 5680d 07h /
17 New directory structure. root 5680d 08h /
16 Fixed a bug in the IN-FIFO - 18 bit samples where not alligned correctly. rudi 7988d 01h /
15 Updated copyright header. rudi 8044d 12h /
14 Fixed a bug reported by Igor. Apparently this bug only shows up when
the WB clock is very low (2x bit_clk). Updated Copyright header.
rudi 8044d 12h /
13 Changed the datasheet and STATUS.txt rudi 8044d 12h /
12 - Added defines to select fifo depth between 4, 8 and 16 entries. rudi 8236d 15h /
11 - fixed spelling rudi 8242d 14h /
10 - Fixed the order of the thrash hold bits to match the spec.
- Many minor synthesis cleanup items ...
rudi 8242d 14h /
9 *** empty log message *** rudi 8262d 09h /
8 Simulation Makefile rudi 8262d 10h /
7 Added test bench for public release rudi 8262d 10h /
6 - Removed RTY_O output.
- Added Clock and Reset Inputs to documentation.
- Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
rudi 8449d 11h /
5 Added Directory Tree Description to README file rudi 8452d 10h /
4 - Changed to new directory structure rudi 8456d 12h /
3 This commit was manufactured by cvs2svn to create tag 'start'. 8532d 16h /
2 Initial Checkin rudi 8532d 16h /

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