URL https://opencores.org/ocsvn/pairing/pairing/trunk

Subversion Repositories pairing

[/] [pairing/] - Rev 27

Rev	Log message	Author	Age	Path
27	definition for undefined wire	homer.xing	4607d 01h	/pairing
26	Detailed description for the ModelSim macro file and the main test bench file	homer.xing	4612d 21h	/pairing
25	simulation scripts and readme-file explaining how to start the simulation	homer.xing	4612d 21h	/pairing
24	LGPL claim in each source hdl file	homer.xing	4620d 21h	/pairing
23	LGPL license text	homer.xing	4620d 21h	/pairing
22	Change TAB to space	homer.xing	4620d 23h	/pairing
21	Add detailed input data capture condition in the document	homer.xing	4620d 23h	/pairing
20	Add a module and a testbench for Xilinx ISE post-route simulation	homer.xing	4622d 01h	/pairing
19	Update synthesis result	homer.xing	4622d 19h	/pairing
18	add synthesis result	homer.xing	4622d 19h	/pairing
17	use logic for $f3m_mux6$	homer.xing	4622d 20h	/pairing
16	Add synthesis configuration files	homer.xing	4623d 00h	/pairing
15	add document. ha ha ha	homer.xing	4623d 01h	/pairing
14	Move constraint file	homer.xing	4623d 01h	/pairing
13	Add document and synthesis directories	homer.xing	4623d 01h	/pairing
12	Simplify the interface of the core.	homer.xing	4623d 02h	/pairing
11	Cheers! as fast as a rocket	homer.xing	4623d 22h	/pairing
10	Ho ho, better circuit	homer.xing	4624d 16h	/pairing
9	Add constrains file for ISE	homer.xing	4625d 19h	/pairing
8	Finished Tate Pairing. Ha ha ha	homer.xing	4625d 20h	/pairing