OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_24/] [or1200/] [rtl] - Rev 1206

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1069 Signal scanb_eni renamed to scanb_en mohor 8008d 22h /or1k/tags/rel_24/or1200/rtl
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 8016d 00h /or1k/tags/rel_24/or1200/rtl
1055 Removed obsolete comment. lampret 8047d 17h /or1k/tags/rel_24/or1200/rtl
1054 Fixed a combinational loop. lampret 8047d 17h /or1k/tags/rel_24/or1200/rtl
1053 Disabled cache inhibit atttribute. lampret 8047d 17h /or1k/tags/rel_24/or1200/rtl
1038 Fixed a typo, reported by Taylor Su. lampret 8055d 01h /or1k/tags/rel_24/or1200/rtl
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 8055d 14h /or1k/tags/rel_24/or1200/rtl
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8056d 01h /or1k/tags/rel_24/or1200/rtl
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8056d 15h /or1k/tags/rel_24/or1200/rtl
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8059d 19h /or1k/tags/rel_24/or1200/rtl

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.