URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] - Rev 78

Rev	Log message	Author	Age	Path
58	made fifo full a warning	JonasDC	4236d 17h	/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4236d 17h	/
56	this is a branch to test performance of a new style of ram	JonasDC	4236d 20h	/
55	updated resource usage in comments	JonasDC	4237d 16h	/
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4237d 17h	/
53	correctly inferred ram for altera dual port ram	JonasDC	4237d 23h	/
52	correct inferring of blockram, no additional resources.	JonasDC	4238d 00h	/
51	true dual port ram for xilinx	JonasDC	4238d 00h	/
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4238d 00h	/
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4249d 19h	/