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Rev Log message Author Age Path
78 removed unsupported fpga jt_eaton 5069d 20h /
77 now generate syn and cov Makefiles
leave log and out files in sim/run directory
jt_eaton 5069d 21h /
76 added wave.save files
now generate sims Makefile and params.sim
leave sim log and vcd files in sim/run/directory
jt_eaton 5072d 02h /
75 added linting using verilator jt_eaton 5075d 18h /
74 split out sw Makefile into projects /bin
split out _cpu into seperate component
jt_eaton 5080d 23h /
73 removed dup png files jt_eaton 5088d 23h /
72 split T6502 into components
moved io_module into seperate project
removed liblists
direct loads filelists for sims and coverage
add hier type into xml files to generate verilog
jt_eaton 5089d 01h /
71 ignore anything in work jt_eaton 5095d 18h /
70 ignore work jt_eaton 5095d 18h /
69 added work dir jt_eaton 5095d 18h /

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