URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] - Rev 571

Rev	Log message	Author	Age	Path
358	Fixed virtual silicon single-port rams instantiation.	lampret	8346d 23h	/or1k/tags/rel_15/or1200/rtl/verilog/
357	Fixed dbg_is_o assignment width.	lampret	8346d 23h	/or1k/tags/rel_15/or1200/rtl/verilog/
356	Break point bug fixed	simons	8347d 02h	/or1k/tags/rel_15/or1200/rtl/verilog/
354	Fixed width of du_except.	lampret	8347d 19h	/or1k/tags/rel_15/or1200/rtl/verilog/
353	Cashes disabled.	simons	8348d 06h	/or1k/tags/rel_15/or1200/rtl/verilog/
352	OR1200_REGISTERED_OUTPUTS can now be enabled.	lampret	8349d 09h	/or1k/tags/rel_15/or1200/rtl/verilog/
351	Fixed some l.trap typos.	lampret	8349d 10h	/or1k/tags/rel_15/or1200/rtl/verilog/
350	For GDB changed single stepping and disabled trap exception.	lampret	8349d 12h	/or1k/tags/rel_15/or1200/rtl/verilog/
338	Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)	lampret	8354d 10h	/or1k/tags/rel_15/or1200/rtl/verilog/
337	Fixed tick timer interrupt reporting by using TTCR[IP] bit.	lampret	8354d 10h	/or1k/tags/rel_15/or1200/rtl/verilog/