URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_17/] [or1200/] [rtl/] - Rev 1780

Rev	Log message	Author	Age	Path
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7844d 17h	/or1k/tags/rel_17/or1200/rtl/
1112	Updated sensitivity list for trace buffer [only relevant for Xilinx FPGAs]	lampret	7919d 15h	/or1k/tags/rel_17/or1200/rtl/
1104	Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.	lampret	7964d 09h	/or1k/tags/rel_17/or1200/rtl/
1083	SB mem width fixed.	simons	7996d 04h	/or1k/tags/rel_17/or1200/rtl/
1079	RAMs wrong connected to the BIST scan chain.	mohor	8005d 01h	/or1k/tags/rel_17/or1200/rtl/
1078	Previous check-in was done by mistake.	mohor	8005d 03h	/or1k/tags/rel_17/or1200/rtl/
1077	Signal scanb_sen renamed to scanb_en.	mohor	8005d 03h	/or1k/tags/rel_17/or1200/rtl/
1069	Signal scanb_eni renamed to scanb_en	mohor	8008d 20h	/or1k/tags/rel_17/or1200/rtl/
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	8015d 22h	/or1k/tags/rel_17/or1200/rtl/
1055	Removed obsolete comment.	lampret	8047d 15h	/or1k/tags/rel_17/or1200/rtl/