OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_23/] [or1200/] - Rev 1069

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8078d 23h /or1k/tags/rel_23/or1200/
960 Directory cleanup. lampret 8078d 23h /or1k/tags/rel_23/or1200/
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8079d 22h /or1k/tags/rel_23/or1200/
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8081d 23h /or1k/tags/rel_23/or1200/
943 Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers. lampret 8081d 23h /or1k/tags/rel_23/or1200/
942 Delayed external access at page crossing. lampret 8081d 23h /or1k/tags/rel_23/or1200/
916 MAC now follows software convention (signed multiply instead of unsigned). lampret 8094d 03h /or1k/tags/rel_23/or1200/
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8110d 06h /or1k/tags/rel_23/or1200/
871 Generic flip-flop based memory macro for register file. lampret 8146d 12h /or1k/tags/rel_23/or1200/
870 Added defines for enabling generic FF based memory macro for register file. lampret 8146d 12h /or1k/tags/rel_23/or1200/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.