URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [rtl/] - Rev 110

Rev	Log message	Author	Age	Path
63	Added additional testcase and changed rst name in BIST to trst	mihad	8022d 00h	/pci/tags/rel_10/rtl/
62	Added BIST signals for RAMs.	mihad	8024d 17h	/pci/tags/rel_10/rtl/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8032d 17h	/pci/tags/rel_10/rtl/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8032d 19h	/pci/tags/rel_10/rtl/
58	Removed all logic from asynchronous reset network	mihad	8037d 19h	/pci/tags/rel_10/rtl/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8038d 01h	/pci/tags/rel_10/rtl/
56	Number of state bits define was removed	mihad	8038d 15h	/pci/tags/rel_10/rtl/
55	Changed state machine encoding to true one-hot	mihad	8038d 16h	/pci/tags/rel_10/rtl/
53	Updated for synthesis purposes. Gate level simulation was failing in some configurations	mihad	8071d 21h	/pci/tags/rel_10/rtl/
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	8072d 01h	/pci/tags/rel_10/rtl/