URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_9/] - Rev 91

Rev	Log message	Author	Age	Path
67	Changed BIST signals for RAMs.	tadejm	8015d 20h	/pci/tags/rel_9/
66	Changed empty status generation in pciw_fifo_control.v	mihad	8019d 06h	/pci/tags/rel_9/
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	8022d 04h	/pci/tags/rel_9/
64	The testcase I just added in previous revision repaired	mihad	8022d 07h	/pci/tags/rel_9/
63	Added additional testcase and changed rst name in BIST to trst	mihad	8022d 09h	/pci/tags/rel_9/
62	Added BIST signals for RAMs.	mihad	8025d 01h	/pci/tags/rel_9/
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	8033d 01h	/pci/tags/rel_9/
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	8033d 03h	/pci/tags/rel_9/
58	Removed all logic from asynchronous reset network	mihad	8038d 03h	/pci/tags/rel_9/
57	Added completion expiration test for WB Slave unit. Changed expiration signalling	mihad	8038d 09h	/pci/tags/rel_9/