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[/] [pci/] [tags/] [rel_WB_B3/] - Rev 92

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Rev Log message Author Age Path
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 8015d 10h /pci/tags/rel_WB_B3/
67 Changed BIST signals for RAMs. tadejm 8015d 15h /pci/tags/rel_WB_B3/
66 Changed empty status generation in pciw_fifo_control.v mihad 8019d 02h /pci/tags/rel_WB_B3/
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8022d 00h /pci/tags/rel_WB_B3/
64 The testcase I just added in previous revision repaired mihad 8022d 02h /pci/tags/rel_WB_B3/
63 Added additional testcase and changed rst name in BIST to trst mihad 8022d 04h /pci/tags/rel_WB_B3/
62 Added BIST signals for RAMs. mihad 8024d 21h /pci/tags/rel_WB_B3/
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8032d 21h /pci/tags/rel_WB_B3/
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8032d 22h /pci/tags/rel_WB_B3/
58 Removed all logic from asynchronous reset network mihad 8037d 22h /pci/tags/rel_WB_B3/

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