URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_19/] [bench/] - Rev 164

Rev	Log message	Author	Age	Path
164	initial inport.	simont	7757d 23h	/8051/tags/rel_19/bench
163	initial inport	simont	7757d 23h	/8051/tags/rel_19/bench
157	change data output.	simont	7758d 00h	/8051/tags/rel_19/bench
156	add FREQ paremeter.	simont	7758d 00h	/8051/tags/rel_19/bench
155	add aditional tests.	simont	7758d 00h	/8051/tags/rel_19/bench
130	prepared programs for new timing.	simont	7798d 18h	/8051/tags/rel_19/bench
129	updated...	simont	7798d 18h	/8051/tags/rel_19/bench
125	update, add prescaler, rclk, tclk.	simont	7808d 01h	/8051/tags/rel_19/bench
124	add support for external rom from xilinx ramb4	simont	7808d 01h	/8051/tags/rel_19/bench
120	defines for pherypherals added	simont	7813d 22h	/8051/tags/rel_19/bench
111	Remove instruction cache and wb_interface	simont	7820d 16h	/8051/tags/rel_19/bench
103	rename signals	simont	7821d 20h	/8051/tags/rel_19/bench
97	initial inport	simont	7821d 23h	/8051/tags/rel_19/bench
96	initial import	simont	7821d 23h	/8051/tags/rel_19/bench
84	remove wb_bus_mon	simont	7900d 20h	/8051/tags/rel_19/bench
74	add module oc8051_wb_iinterface	simont	7977d 18h	/8051/tags/rel_19/bench
68	add instruction cache and DELAY parameters for external ram, rom	simont	7981d 21h	/8051/tags/rel_19/bench
59	add external rom	simont	7988d 16h	/8051/tags/rel_19/bench
46	prepared header	simont	8005d 17h	/8051/tags/rel_19/bench
37	added signals ack, stb and cyc	simont	8032d 20h	/8051/tags/rel_19/bench