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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 94

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Rev Log message Author Age Path
94 temp version. Resets will be changed in next version. mohor 7535d 06h /dbg_interface/tags/asyst_2/rtl
93 tmp version. mohor 7536d 07h /dbg_interface/tags/asyst_2/rtl
92 temp version. mohor 7539d 11h /dbg_interface/tags/asyst_2/rtl
91 tmp version. mohor 7540d 06h /dbg_interface/tags/asyst_2/rtl
90 tmp version. mohor 7541d 01h /dbg_interface/tags/asyst_2/rtl
89 temp4 version. mohor 7542d 07h /dbg_interface/tags/asyst_2/rtl
88 temp3 version. mohor 7543d 01h /dbg_interface/tags/asyst_2/rtl
87 tmp2 version. mohor 7544d 06h /dbg_interface/tags/asyst_2/rtl
86 Tmp version. mohor 7557d 02h /dbg_interface/tags/asyst_2/rtl
83 Small fix. mohor 7557d 03h /dbg_interface/tags/asyst_2/rtl
82 New directory structure. New version of the debug interface. mohor 7557d 03h /dbg_interface/tags/asyst_2/rtl
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7557d 03h /dbg_interface/tags/asyst_2/rtl
77 MBIST chain connection fixed. mohor 7618d 00h /dbg_interface/tags/asyst_2/rtl
73 CRC logic changed. mohor 7618d 02h /dbg_interface/tags/asyst_2/rtl
71 Mbist support added. simons 7620d 09h /dbg_interface/tags/asyst_2/rtl
67 Lower two address lines must be always zero. simons 7653d 04h /dbg_interface/tags/asyst_2/rtl
65 WB_CNTL register added, some syncronization fixes. simons 7654d 04h /dbg_interface/tags/asyst_2/rtl
63 Three more chains added for cpu debug access. simons 7674d 05h /dbg_interface/tags/asyst_2/rtl
61 Lapsus fixed. simons 7702d 04h /dbg_interface/tags/asyst_2/rtl
59 Reset value for riscsel register set to 1. simons 7702d 05h /dbg_interface/tags/asyst_2/rtl

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