OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_10/] [bench/] [verilog/] - Rev 154

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5653d 01h /pci/tags/rel_10/bench/verilog
125 This commit was manufactured by cvs2svn to create tag 'rel_10'. 7617d 00h /pci/tags/rel_10/bench/verilog
122 mbist signals updated according to newest convention markom 7624d 00h /pci/tags/rel_10/bench/verilog
119 Added support for WB B3. Some testcases were updated. tadejm 7680d 12h /pci/tags/rel_10/bench/verilog
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7693d 17h /pci/tags/rel_10/bench/verilog
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7698d 15h /pci/tags/rel_10/bench/verilog
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7704d 01h /pci/tags/rel_10/bench/verilog
92 Update! mihad 7751d 07h /pci/tags/rel_10/bench/verilog
89 Burst 2 error fixed. mihad 7822d 21h /pci/tags/rel_10/bench/verilog
87 Updated acording to RTL changes. mihad 7840d 18h /pci/tags/rel_10/bench/verilog
81 Updated synchronization in top level fifo modules. mihad 7883d 11h /pci/tags/rel_10/bench/verilog
73 Bug fixes, testcases added. mihad 7892d 17h /pci/tags/rel_10/bench/verilog
69 Changed BIST signal names etc.. mihad 7984d 20h /pci/tags/rel_10/bench/verilog
66 Changed empty status generation in pciw_fifo_control.v mihad 7991d 21h /pci/tags/rel_10/bench/verilog
64 The testcase I just added in previous revision repaired mihad 7994d 21h /pci/tags/rel_10/bench/verilog
63 Added additional testcase and changed rst name in BIST to trst mihad 7994d 23h /pci/tags/rel_10/bench/verilog
62 Added BIST signals for RAMs. mihad 7997d 16h /pci/tags/rel_10/bench/verilog
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8010d 23h /pci/tags/rel_10/bench/verilog
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8044d 16h /pci/tags/rel_10/bench/verilog
52 Oops, never before noticed that OC header is missing mihad 8045d 00h /pci/tags/rel_10/bench/verilog

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.