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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5679d 12h /dbg_interface/trunk/rtl/verilog
152 CTRL READ fixed. Stall bit was not shifted out OK. Error appeared in last
check-in.		 igorm 7476d 18h /dbg_interface/trunk/rtl/verilog
150 Zero is shifted out when CTRL_READ command is active. igorm 7477d 12h /dbg_interface/trunk/rtl/verilog
147 CPU_WR_CTRL and CPU_RD_CTRL defines changed. igorm 7479d 18h /dbg_interface/trunk/rtl/verilog
146 Changes for the FormalPRO. igorm 7483d 15h /dbg_interface/trunk/rtl/verilog
144 Port names and defines for the supported CPUs changed. igorm 7483d 20h /dbg_interface/trunk/rtl/verilog
143 Signals for easier debugging removed. igorm 7483d 21h /dbg_interface/trunk/rtl/verilog
141 data_cnt_lim length changed to reduce number of warnings. igorm 7484d 17h /dbg_interface/trunk/rtl/verilog
139 New release of the debug interface (3rd. release). igorm 7487d 11h /dbg_interface/trunk/rtl/verilog
138 Temp version before changing dbg interface. igorm 7493d 15h /dbg_interface/trunk/rtl/verilog
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7545d 21h /dbg_interface/trunk/rtl/verilog
123 All flipflops are reset. mohor 7550d 18h /dbg_interface/trunk/rtl/verilog
121 Port signals are all set to zero after reset. mohor 7553d 18h /dbg_interface/trunk/rtl/verilog
119 cpu_stall_o activated as soon as bp occurs. mohor 7553d 22h /dbg_interface/trunk/rtl/verilog
117 Define name changed. mohor 7555d 17h /dbg_interface/trunk/rtl/verilog
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7557d 00h /dbg_interface/trunk/rtl/verilog
106 Sensitivity list updated. simons 7557d 22h /dbg_interface/trunk/rtl/verilog
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7558d 13h /dbg_interface/trunk/rtl/verilog
102 New version. mohor 7558d 14h /dbg_interface/trunk/rtl/verilog
101 Almost finished. mohor 7558d 15h /dbg_interface/trunk/rtl/verilog

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